The field of the present invention relates generally to semiconductor fabrication and, more particularly, to transistors with polysilicon-silicide gates.
In device fabrication, insulating, semiconducting, and conducting layers are formed on a substrate. The layers are patterned to create features and spaces. The features and spaces are patterned so as to form devices, such as transistors, capacitors, and resistors. These devices are then interconnected to achieve a desired electrical function, creating an integrated circuit (IC).
To reduce sheet resistance, a metal oxide semiconductor (MOS) transistor employs a polycide gate. The polycide gate comprises metal silicide, such as tungsten silicide (WSix) over heavily doped polysilicon (poly). Typically, the poly is doped with phosphorus (P). The poly should contain as high a dopant concentration as possible to lower its sheet resistance.
However, metal silicide over heavily doped poly shows stoichiometric control problems, which are expressed in the form of a metallic-rich interface. A metallic-rich interface is undesirable since it is not resistant to subsequent thermal processes. As a result, the interface gets oxidized. Oxidation causes surface roughness and, in some cases, delamination of the silicide film. As such, the interface between the poly and silicide should be maintained below a level which produces a metallic-rich interface. Typically, the P concentration should be kept below 1019 atoms/cm3.
Conventionally, the adverse effects of metallic rich interface are avoided by providing an intrinsic (undoped) layer of poly between the heavily doped poly and the metal silicide. Another technique that avoids a metal-rich interface is to lower the dopant concentration of the poly. However, such techniques undesirably increase gate resistance, resulting in decreased device performance.
From the above description, it is desirable to provide a reliable polycide gate with reduced sheet resistance.
The invention relates to formation of a reliable gate conductor with decreased thickness and lower sheet resistance. In one embodiment, the decreased thickness and lower sheet resistance are achieved by forming a heavily doped poly layer and annealing it to diffuse dopants out from the surface thereof to decrease the dopant concentration to below that which causes metal rich interface. This allows a metal silicide layer to be deposited without an intrinsic cap poly layer or requiring the poly to having a lower dopant concentration.